תאור התפקיד
In your role you will be responsible for Developing understanding of the design architecture and contributing at multiple levels on the micro-architecture features and specification. Implementing block/sub-system level logic design RTL using Verilog. Working with pre-silicon validation engineers to validate the design and fix design bugs. You must be a team player, willing to go the extra mile to achieve success.
דרישות התפקיד
BSc or Msc in Electrical and Electronic engineering from a known university (Technion, TA, Ben Gurion) – MUST
4+ years of experience in VLSI RTL– Must
Scripting knowledge in TCL – Must
Team player with excellent oral and written communication skills
Ability to quickly learn new skills, adapt to change and enter new technical fields
Knowledge in DFT – and Advantage
Knowledge in Cryptography / Security – an advantage
Familiarity with the following tools : Design Compiler, ICC, Primetime, Formality, Tetramax– an advantage
Familiarity with RTL to GDS full flow implementation – an advantage
Experience with small geometry process node ( 65nm and below ) – an advantage.
