VLSI Design Manager with experience in leading design team
דרישות התפקיד
Education: BSc in Electronics engineering/communication system engineer/ Computer Engineering. Grades: Tel Aviv-82+, Beer Sheva–85+, Technion-81. Language Knowledge: Verilog and system Verilog Experience: 2-4 years of experience as a VLSI Designer – including writing and ownership on a complex Verilog blocks for ASIC with tight frequency, area and power requirements. Working on a full design flow from high-level architecture definitions, through micro ARCH , Verilog writing and verification process up to timing closure and STA 2-4 years of experience as a VLSI design team leader – including managing 3-5 engineers in a tightly schedule high complexity design through the entire VLSI flow.
