Verification/Logic Design Engineer

תאור התפקיד

Verification Engineer for VLSI Department- Experienced and Junior

דרישות התפקיד

Education: BSc in HW engineering or Electronics engineering from one of the following universities

Tel-Aviv, Beer sheva, Technion

Grades: Tel Aviv-82+, Beer Sheva-85+, Technion-81+

Experience:

0-5 years of experience in Advanced ASIC RTL Design (not verification component)

Advantages:

·         Knowledge in: Verilog & simulation, perl & TCL scripts, Linux

·         Experience in processor design or memory subsystem design.

·         Experience in low power technics in RTL level.