Senior VLSI Engineer לחברה מבטיחה באזור ירושלים

דרישות התפקיד

BSc in Electrical Engineering.

At least 3 years of experience in working with Verilog/synthesis to explore and optimize floor-planning at block and system levels.

Can work with Design-Compiler-Topographical flow.

Capability to derive timing constraints and exceptions for multiple clock domains in the SoC.

Good Tcl scripting skills.

Place-And-Rout and/or Clock-Tree-Synthesis experience – advantage.

Experienced with large SoC complexities and challenges – advantage.

Experience with TSMC advanced technology nodes – advantage.